High dielectric constant spacer for imagers

ABSTRACT

An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency.

FIELD OF THE INVENTION

The invention relates generally to a method and apparatus relating to apixel array of an imager. In particular, the invention relates toimagers having pixels with an improved gate structure.

BACKGROUND

Typically, a digital imager array includes a focal plane array of pixelcells, each one of the cells including a photoconversion device, e.g. aphotogate, photoconductor, or a photodiode. In a CMOS imager a readoutcircuit is connected to each pixel cell which typically includes asource follower output transistor. The photoconversion device convertsphotons to electrons which are typically transferred to a floatingdiffusion region connected to the gate of the source follower outputtransistor. A charge transfer device (e.g., transistor) can be includedfor transferring charge from the photoconversion device to the floatingdiffusion region. In addition, such imager cells typically have atransistor for resetting the floating diffusion region to apredetermined charge level prior to charge transference. The output ofthe source follower transistor is gated as an output signal by a rowselect transistor.

Exemplary CMOS imaging circuits, processing steps thereof, and detaileddescriptions of the functions of various CMOS elements of an imagingcircuit are described, for example, in U.S. Pat. No. 6,140,630 toRhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 toRhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No.6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. Thedisclosures of each of the forgoing patents are hereby incorporated byreference in their entirety.

FIG. 1 illustrates a block diagram of an exemplary CMOS imager device308 having a pixel array 200 with each pixel cell being constructed asdescribed above. Pixel array 200 comprises a plurality of pixelsarranged in a predetermined number of columns and rows (not shown). Thepixels of each row in array 200 are all turned on at the same time by arow select line, and the pixels of each column are selectively output byrespective column select lines. A plurality of row and column lines areprovided for the entire array 200. The row lines are selectivelyactivated by a row driver 210 in response to row address decoder 220.The column select lines are selectively activated by a column driver 260in response to column address decoder 270. Thus, a row and columnaddress is provided for each pixel. The CMOS imager is operated by thetiming and control circuit 250, which controls address decoders 220, 270for selecting the appropriate row and column lines for pixel readout.The control circuit 250 also controls the row and column drivercircuitry 210, 260 such that these apply driving voltages to the drivetransistors of the selected row and column lines. The pixel columnsignals, which typically include a pixel reset signal (V_(rst)) and apixel image signal (V_(sig)), are read by a sample and hold circuit 261associated with the column device 260. A differential signal(V_(rst)−V_(sig)) is produced by differential amplifier 262 for eachpixel which is digitized by analog-to-digital converter 275 (ADC). Theanalog-to-digital converter 275 supplies the digitized pixel signals toan image processor 280, which forms a digital image.

In a digital CMOS imager, when incident light strikes the surface of aphotoconversion device, e.g., a photodiode, electron/hole pairs aregenerated in the p-n junction of the photodiode. The generated electronsare collected in the n-type region of the photodiode. The photo chargemoves from the initial charge accumulation region to the floatingdiffusion region or it may be transferred to the floating diffusionregion via a transfer transistor. The charge at the floating diffusionregion is typically converted to a pixel output voltage by a sourcefollower transistor (described above).

Image lag can be a problem for imagers, whether the imager is a CMOS,CCD or other type of imager. Image lag can occur, for example, in CMOSimage sensor pixels using transfer transistors to transfer charge fromthe photodiode to the floating diffusion region. There is a potentialbarrier corresponding to the photodiode/transfer gate region. If thispotential barrier is too high, a portion of the charge will be unable tomove from the photodiode to the floating diffusion region. The greaterthe potential barrier, the less charge will be transferred to thefloating diffusion region. A potential barrier in thephotodiode/transfer gate region may cause incomplete charge transferreducing the charge transfer efficiency (CTE) of the pixel cell. Chargeremaining in the photodiode from a prior image can affect a subsequentimage, causing image lag, where a ghost image from the initial charge isapparent in a subsequent image.

Fringing fields improve charge transfer from a photoconversion device,e.g. a photodiode, to a charge collection region. Conventional imagerstypically utilize low dielectric (K) oxide spacers for transistor gates,which create smaller fringing fields. A larger fringing field in, forexample, a transfer gate of a CMOS imager would improve charge transferfrom the photodiode to the floating diffusion region. This would therebyreduce image lag because more carriers are transferred. In CCD imagers,larger fringing fields improve charge transfer efficiency (CTE) inaddition to improving image lag characteristics.

CCD devices that use overlapping polysilicon 1 and polysilicon 2electrodes achieve a high fringing field by applying high voltages tothe polysilicon electrodes. This is not desireable on CMOS imagers whichare advantageously low voltage devices so they will compatible with CMOSlogic circuit and devices. Another imager device, the single polysiliconCCD imager does not have overlapping polysilicon electrodes and couldalso benefit from a method to achieve high fringing fields to achieveimproved charge transfer. Thus, there is a desire and need to increasefringing fields and thereby improve charge transfer and reduce image lagin imager devices.

SUMMARY

Embodiments of the invention provide an imager having gates with spacersformed of a high dielectric constant material. The high dielectricspacers provide larger fringing fields for charge transfer and alsoimprove image lag and charge transfer efficiency.

DESCRIPTION OF THE DRAWINGS

Additional features of the present invention will be apparent from thefollowing detailed description and drawings which illustrate exemplaryembodiments of the invention, in which:

FIG. 1 is a block diagram of a conventional imager device having a pixelarray;

FIG. 2 is a cross-sectional view of a portion of a pixel of an imagesensor according to an embodiment of the invention;

FIG. 3 shows a cross-sectional view of a portion of the FIG. 2photodiode during an initial stage of processing performed in accordancewith a method of the invention;

FIG. 4 shows a stage of processing subsequent to that shown in FIG. 3;

FIG. 5 shows a stage of processing subsequent to that shown in FIG. 4;

FIG. 6 shows a stage of processing subsequent to that shown in FIG. 5;

FIG. 7 shows a stage of processing subsequent to that shown in FIG. 6;

FIG. 8 shows a stage of processing subsequent to that shown in FIG. 7;

FIG. 9 shows a stage of processing subsequent to that shown in FIG. 8;

FIG. 10 shows a stage of processing subsequent to that shown in FIG. 9;

FIG. 11 is a cross-sectional view of a portion of a pixel of an imagesensor according to another embodiment of the invention;

FIGS. 12 a, 12 b and 12 c are cross-sectional views of a portion of apixel of an image sensor according to another embodiment of theinvention; and

FIG. 13 is a schematic diagram of a processing system employing animager constructed in accordance with any of the various embodiments ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and show by way ofillustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical, and electrical changes may be made withoutdeparting from the spirit and scope of the present invention. Theprogression of processing steps described is exemplary of embodiments ofthe invention; however, the sequence of steps is not limited to that setforth herein and may be changed as is known in the art, with theexception of steps necessarily occurring in a certain order.

The terms “wafer” and “substrate,” as used herein, are to be understoodas including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire(SOS) technology, doped and undoped semiconductors, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processingsteps may have been utilized to form regions, junctions, or materiallayers in or over the base semiconductor structure or foundation. Inaddition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, gallium arsenide or othersemiconductors.

The term “pixel,” as used herein, refers to a photo-element unit cellcontaining a photoconversion device and associated transistors forconverting photons to an electrical signal. For purposes ofillustration, a single representative pixel and its manner of formationis illustrated in the figures and description herein; however, typicallyfabrication of a plurality of like pixels proceeds simultaneously.Accordingly, the following detailed description is not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims.

In the following description, the invention is described in relation toCMOS and CCD imagers for convenience; however, the invention has widerapplicability to other solid state imagers. Now referring to thefigures, where like reference numbers designate like elements, FIG. 2illustrates a pixel sensor cell of a CMOS imager constructed inaccordance with a first exemplary embodiment of the invention. Aphotoconversion device 50 is formed in a substrate 60 having a dopedlayer or well 61, which for exemplary purposes is a p-type well. Theillustrated photoconversion device 50 is a photodiode and may be a p-njunction photodiode, npn photodiode, a photoconductor, a Schottkyphotodiode, or any other suitable photodiode, but for exemplary purposesis discussed as a p-n-p photodiode. In addition and for exemplarypurposes only, substrate 60 is a p-type substrate and well 61 is ap-type well.

The illustrated photodiode 50 consists of a p+region 22 and an n-typeregion 24. The remaining structures shown in FIG. 2 include a transfertransistor with associated gate 26 and a reset transistor withassociated gate 28. Floating diffusion region 16, source/drain region 30and shallow trench isolation (STI) regions 55 are also shown. A sourcefollower transistor 40 and row select transistor 42 with associatedgates are also included in the pixel sensor cell, but are depicted inelectrical schematic form with the output of the row select transistor40 being connected with a column line 31. Although shown in FIG. 2 as afour-transistor (4T) configuration with a transfer transistor andassociated gate 26, the invention can also be utilized in athree-transistor (3T) configuration, without a transfer transistor, andin pixels with other transistor configurations (e.g., 2T, 5T, 6T, 7T,etc.).

In the exemplary embodiment shown in FIG. 2, a high dielectric constantmaterial is used for the spacer layers 43 of the transfer transistor andassociated gate 26. Although shown in this embodiment as being utilizedin association with a transfer transistor, the high dielectric constantspacers may be used as spacer material for any other transistor in theimage sensor. Any suitable material having a high dielectric constantmay be used for the spacer layer 43. The spacer material should be aninsulator material and should have a dielectric constant higher thansilicon dioxide. Examples of high dielectric constant materials whichmay be used to form the spacer layer 43 are materials having adielectric constant of greater than 3.9, and including but not limitedto, aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide(Ta₂O₃), barium strontium titanate ((BaSr)TiO₃ also known as BST) andsilicon nitride (Si₃N₄).

FIGS. 3-10 show one exemplary method of forming a pixel sensor cell witha high dielectric constant spacer of FIG. 2 of the invention at variousstages of formation. For convenience, the same cross-sectional view ofFIG. 2 is utilized in FIGS. 3-10 for the ensuing description. Inaddition, for clarity purposes, the source follower and row selecttransistors 40, 42 (FIG. 2) are not illustrated but it should beappreciated that they are present in the final pixel sensor cell.

Referring to FIG. 3, first a p-type silicon substrate 60 is provided.Isolation regions 55 are formed to electrically isolate regions of thesubstrate where pixel cells will later be formed. The isolation regions55, can be formed by any known technique such as thermal oxidation ofthe underlying silicon in a LOCOS process, or by etching trenches andfilling them with oxide in an STI (shallow trench isolation) process.

FIG. 4 shows a blanket deposition of a gate oxide layer 38 oversubstrate 60. FIGS. 4-9 show the formation of one exemplary gate stack15 for a transfer transistor which has high dielectric constant (high K)spacers according to an embodiment of the invention. However, more thanone gate stack with high K spacers constructed according to theinvention may also be formed. For example, embodiments of the inventionmay be employed on storage transistors, high dynamic range transistors,source follower transistors, row select transistors or global shuttertransistors. Gate stacks 15 and 19 are formed over gate oxide layer 38by conventional methods and have an insulator layer 34 and conductorlayer 36. Conductor layer 36 may be formed of any conductive materialand insulator layer 34 may be formed of any insulating material known inthe art. The conductor 36 is, for example, poly, polysilicide,poly/WSix₂, poly TiSi₂, poly/WNx/W. The insulator layer may be oxide ora high K material or a sandwich structure of these insulators. Theinsulator layer 34 is not required.

As shown in FIG. 5, if the p-type well 61 has not yet been formed, itmay be formed by blanket implantation or by masked implantation. P-typewell 61 may be formed before or after the formation of isolation regions55 and gate stack 15. The p-well implant may be conducted so that thepixel array well 61 and a p-type periphery logic well, which willcontain logic circuits for controlling the pixel array, have differentdoping profiles. As known in the art, multiple high energy implants maybe used to tailor the profile and position of the p-type well 61. Thep-type well shown in FIG. 5 is shown as a p-type well formed using amasked ion implantation.

Formed floating diffusion region 16 and source/drain region 30 aredepicted in FIG. 6. The doped regions 16, 30 are formed in the p-well 61and are doped to an n-type conductivity in this embodiment. Forexemplary purposes, regions 16, 30 are n+ doped to form an n-channelgate transistor, however, regions 16 and 30 may also be p-type doped toform a p-channel gate transistor. Regions 16, 30 may be formed byapplying a mask to the substrate and doping the regions 16, 30 by ionimplantation. FIG. 6 also shows n-type implantation of region 24 bymethods known in the art. Doped region 16 could also be a n-implantedregion.

FIG. 7 shows the deposition of a high K dielectric layer 43 over gatestacks 15, 19 and gate oxide layer 38. Layer 43 may be formed of anymaterial having high dielectric constant properties, including forexample, aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), silicon nitride(Si₃N₄), tantalum oxide (Ta₂O₃), and barium strontium titanate((BaSr)TiO₃). A dual high dielectric constant material spacer may alsobe used. The thickness of the high K dielectric layer 43 may be in therange of about 100 Å to about 1500 Å, preferably in the range of about200 Å to about 800 Å. A high dielectric constant material used on thespacers of a transistor, in this embodiment a transfer transistor,creates a larger fringing field in the gate channel of the transistor.The larger fringing field produced by the high dielectric constantspacer on the transfer transistor gate 26 improves charge transfer fromthe photodiode 50 to the floating diffusion region 16 and reduces imagelag.

FIG. 8 shows implantation of p-type region 22 of photodiode 50. Theimplantation of p-type region 22 may occur by methods known in the art.A masked spacer etch with mask 45, as illustrated in FIG. 9, isperformed to remove the high dielectric constant material, except forareas covered by mask 45, including a portion of gate stacks 15, 19 onone side and on a sidewall of gate stacks 15, 19 on the opposite side.The masked spacer etch step leaves areas of the transfer transistor andassociated gate 26 and a sidewall covered with the high dielectricconstant layer 43, as shown in FIG. 10. Although described above inconjunction with FIGS. 9 and 10 as a masked spacer etch step, the spaceretch could also be performed without a mask 45. FIG. 10 also shows aformed reset transistor and associated gate 28.

The reset transistor or any other transistor may also be formed with orwithout a high dielectric constant spacers. Alternatively, sometransistors of a pixel sensor cell may be formed with a high dielectricconstant spacers, while other transistors of the same pixel sensor cellmay be formed according to conventional methods with conventionalspacers known in the art. In addition, although described above inreference to a CMOS image sensor, the method of forming a gate stackhaving a high dielectric constant spacer may also be performed on othertypes of imagers such as for example, a charge coupled device (CCD).

The pixel sensor cell is essentially complete at this stage, andconventional processing methods may be used to form insulating,shielding, and metallization layers to connect gate lines and otherconnections to the pixel sensor cells. For example, the entire surfacemay be covered with a passivation layer 88 of, for example, silicondioxide, BSG, PSG, or BPSG, which is CMP planarized and etched toprovide contact holes, which are then metallized to provide contacts.Conventional layers of conductors and insulators may also be used tointerconnect the structures and to connect the pixel to peripheralcircuitry.

FIG. 11 shows another embodiment of the invention which is similar tothe embodiment described above in relation to FIGS. 3-10 except that ablanket spacer etch step is used to remove the dielectric layer 43,rather than the masked step shown above in FIG. 9.

FIG. 12 a-c show embodiments of the invention as applied to a CCDimager. For simplicity, only the transistors are shown. FIGS. 12 a and12 b depict a single gate CCD imager with a vertical or horizontal shiftregister. In the embodiment of FIG. 12 a, the high dielectric materialis employed as spacers 25, as described above in relation to FIGS. 3-10except that a blanket spacer etch step is used to remove the dielectriclayer 43, rather than the masked step shown above in FIG. 9. FIG. 12 bshows a single gate CCD imager having high dielectric material assidewalls 27.

FIG. 12 c shows an embodiment according to the invention having anoverlapping gate 32 between two transistor gates on a CCD imager. Theembodiment of FIG. 12 c has a first gate oxide layer 35 and a secondgate oxide layer 33. High dielectric constant spacers 25 are formed asdescribed above in reference to FIGS. 3-10 with the exception of ablanket spacer etch step instead of the masked step shown in FIG. 9. Thegate stacks also have a conductive layer 36 and an insulator layer 34,as described above.

FIG. 13 shows a processor system 300, which includes an imager device308 (FIG. 1) constructed in accordance with an embodiment of theinvention; that is, the imager device 308 uses a pixel array havingpixels constructed in accordance with the various embodiments of theinvention. The imager device 308 may receive control or other data fromsystem 300. System 300 includes a processor 302 having a centralprocessing unit (CPU) that communicates with various devices over a bus304. Some of the devices connected to the bus 304 provide communicationinto and out of the system 300; an input/output (I/O) device 306 andimager device 308 are such communication devices. Other devicesconnected to the bus 304 provide memory, illustratively including arandom access memory (RAM) 310, hard drive 312, and one or moreperipheral memory devices such as a floppy disk drive 314 and compactdisk (CD) drive 316. The imager device 308 may be constructed as shownin FIG. 1 with the pixel array 200 having the characteristics of theinvention as described above in connection with FIGS. 2-12. Theinvention provides an imager having gates with spacers formed of a highdielectric material. The high dielectric spacers provide larger fringingfields for charge transfer and also improve image lag and chargetransfer efficiency. The imager device 308 may, in turn, be coupled toprocessor 302 for image processing, or other image handling operations.

The processes and devices described above illustrate preferred methodsand typical devices of many that could be used and produced. The abovedescription and drawings illustrate embodiments, which achieve theobjects, features, and advantages of the present invention. However, itis not intended that the present invention be strictly limited to theabove-described and illustrated embodiments. Any modifications, thoughpresently unforeseeable, of the present invention that come within thespirit and scope of the following claims should be considered part ofthe present invention.

1. A pixel sensor cell comprising: a photoconversion device; and at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer comprising high dielectric constant material.
 2. The pixel sensor cell of claim 1, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.
 3. The pixel sensor cell of claim 1, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.
 4. The pixel sensor cell of claim 3, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.
 5. The pixel sensor cell of claim 1, wherein said pixel sensor cell is part of a CCD sensor.
 6. The pixel sensor cell of claim 5, wherein the CCD sensor is a single gate CCD sensor.
 7. The pixel sensor cell of claim 5, wherein the CCD sensor is an overlapping gate sensor.
 8. The pixel sensor cell of claim 1, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.
 9. The pixel sensor cell of claim 8, wherein said photodiode is a pnp photodiode.
 10. The pixel sensor cell of claim 8, wherein said photodiode is an npn photodiode.
 11. The pixel sensor cell of claim 1, wherein said gate stack is part of an n-channel transistor.
 12. The pixel sensor cell of claim 1, wherein said gate stack is part of a p-channel transistor.
 13. The pixel sensor cell of claim 1, wherein said gate stack is formed of a gate oxide layer and a conductor layer.
 14. The pixel sensor cell of claim 1, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.
 15. The pixel sensor cell of claim 13, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.
 16. The pixel sensor cell of claim 14, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 17. The pixel sensor cell of claim 13, wherein said gate oxide layer is a grown layer.
 18. The pixel sensor cell of claim 17 wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.
 19. The pixel sensor cell of claim 13, wherein said gate oxide layer is a deposited layer.
 20. The pixel sensor cell of claim 19, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 21. The pixel sensor cell of claim 1, wherein said high dielectric constant material spacer has a thickness of about 100 Åto about 1500 Å.
 22. The pixel sensor cell of claim 1, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.
 23. The pixel sensor cell of claim 1, wherein said pixel sensor cell is part of a CMOS imager.
 24. An imager integrated circuit comprising: a doped layer formed in a substrate; an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material; and signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing pixel signals representing an image acquired by the array and for providing output data representing said image.
 25. The imager integrated circuit of claim 24, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.
 26. The imager integrated circuit of claim 24, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.
 27. The imager integrated circuit of claim 26, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.
 28. The imager integrated circuit of claim 24, wherein said pixel sensor cell is part of a CCD sensor.
 29. The imager integrated circuit of claim 28, wherein the CCD sensor is a single gate CCD sensor.
 30. The imager integrated circuit of claim 28, wherein the CCD sensor is an overlapping gate sensor.
 31. The imager integrated circuit of claim 24, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.
 32. The imager integrated circuit of claim 31, wherein said photodiode is a pnp photodiode.
 33. The imager integrated circuit of claim 31, wherein said photodiode is an npn photodiode.
 34. The imager integrated circuit of claim 24, wherein said gate stack is part of an n-channel transistor.
 35. The imager integrated circuit of claim 24, wherein said gate stack is part of a p-channel transistor.
 36. The imager integrated circuit of claim 24, wherein said gate stack is formed of a gate oxide layer and a conductor layer.
 37. The imager integrated circuit of claim 24, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.
 38. The imager integrated circuit of claim 36, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.
 39. The imager integrated circuit of claim 37, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 40. The imager integrated circuit of claim 36, wherein said gate oxide layer is a grown layer.
 41. The imager integrated circuit of claim 40, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.
 42. The imager integrated circuit of claim 36, wherein said gate oxide layer is a deposited layer.
 43. The imager integrated circuit of claim 42, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 44. The imager integrated circuit of claim 24, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.
 45. The imager integrated circuit of claim 24, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.
 46. The imager integrated circuit of claim 24, wherein said pixel sensor cell is part of a CMOS imager.
 47. A processing system comprising: a processor; and an imager coupled to said processor, having pixel sensor cells, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material.
 48. The system of claim 47, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.
 49. The system of claim 47, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.
 50. The system of claim 49, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.
 51. The system of claim 47, wherein said pixel sensor cell is part of a CCD sensor.
 52. The system of claim 51, wherein the CCD sensor is a single gate CCD sensor.
 53. The system of claim 51, wherein the CCD sensor is an overlapping gate sensor.
 54. The system of claim 47, wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photo sensor.
 55. The system of claim 54, wherein said photodiode is a pnp photodiode.
 56. The system of claim 54, wherein said photodiode is an npn photodiode.
 57. The system of claim 47, wherein said gate stack is part of an n-channel transistor.
 58. The system of claim 47, wherein said gate stack is part of a p-channel transistor.
 59. The system of claim 47, wherein said gate stack is formed of a gate oxide layer and a conductor layer.
 60. The system of claim 47, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.
 61. The system of claim 59, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.
 62. The system of claim 60, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 63. The system of claim 59, wherein said gate oxide layer is a grown layer.
 64. The system of claim 63, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.
 65. The system of claim 59, wherein said gate oxide layer is a deposited layer.
 66. The system of claim 65, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 67. The system of claim 47, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.
 68. The system of claim 47, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.
 69. The system of claim 47, wherein said pixel sensor cell is part of a CMOS imager.
 70. A method of forming a pixel sensor cell comprising: forming at least one gate stack; forming a spacer over at least one portion of said at least one gate stack, wherein said spacer is comprised of a high dielectric constant material.
 71. The method of claim 70, wherein said forming a spacer step comprises forming the spacer with a thickness of about 100 Å to about 1500 Å.
 72. The method of claim 70, wherein said forming a spacer step comprises forming the spacer with a thickness of about 200 Å to about 600 Å.
 73. The method of claim 70, further comprising etching said spacer layer.
 74. The method of claim 73, wherein said pixel sensor cell is masked before said etching step.
 75. The method of claim 70, wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.
 76. The method of claim 70, wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.
 77. The method of claim 76, wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.
 78. The method of claim 70, wherein said pixel sensor cell is part of a CCD sensor.
 79. The method of claim 78, wherein the CCD sensor is a single gate CCD sensor.
 80. The method of claim 78, wherein the CCD sensor is an overlapping gate sensor.
 81. The method of claim 70, wherein said gate stack is part of an n-channel transistor.
 82. The method of claim 70, wherein said gate stack is part of a p-channel transistor.
 83. The method of claim 70, wherein said gate stack is formed of a gate oxide layer and a conductor layer.
 84. The method of claim 70, wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.
 85. The method of claim 84, wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.
 86. The method of claim 84, wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 87. The method of claim 83, wherein said gate oxide layer is a grown layer.
 88. The method of claim 87, wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.
 89. The method of claim 83, wherein said gate oxide layer is a deposited layer.
 90. The method of claim 89, wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.
 91. The method of claim 70, wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.
 92. The method of claim 70, wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.
 93. The method of claim 70, wherein said pixel sensor cell is part of a CMOS imager. 